1. Field of the Invention
The present invention relates to an overshoot suppression circuit for a voltage regulator.
2. Description of the Related Art
A conventional voltage regulator is now described. FIG. 4 is a circuit diagram illustrating the conventional voltage regulator.
The conventional voltage regulator includes a reference voltage circuit 101, an error amplifier circuit 102, a bias circuit 103 for the error amplifier circuit 102, a PMOS transistor 104 serving as an output transistor, a voltage dividing resistor circuit 105, an amplifier 301, a bias circuit 302 for the amplifier 301, and a PMOS transistor 108.
The PMOS transistor 104 is connected between a power supply terminal and an output terminal 109. The voltage dividing resistor circuit 105 for outputting a feedback voltage Vfb is connected between the output terminal 109 and a ground terminal. The error amplifier circuit 102 has an inverting input terminal connected to the reference voltage circuit 101, a non-inverting input terminal for inputting the feedback voltage Vfb, and an output terminal connected to a gate of the PMOS transistor 104. The bias circuit 103 supplies an operating current to the error amplifier circuit 102. The PMOS transistor 108 is connected between the power supply terminal and the gate of the PMOS transistor 104. The amplifier 301 has a non-inverting input terminal connected to the reference voltage circuit 101, an inverting input terminal for inputting the feedback voltage Vfb, and an output terminal connected to a gate of the PMOS transistor 108. The bias circuit 302 supplies an operating current to the amplifier 301.
The amplifier 301 compares the input feedback voltage Vfb with a reference voltage Vref. When the feedback voltage Vfb is lower than the reference voltage Vref, the amplifier 301 outputs a Hi signal to turn OFF the PMOS transistor 108. When an overshoot occurs in an output voltage Vout of the output terminal 109 and the feedback voltage Vfb becomes higher than the reference voltage Vref, the amplifier 301 outputs a Lo signal to turn ON the PMOS transistor 108.
The conventional voltage regulator operates in the manner described above to prevent the overshoot in the output voltage Vout of the output terminal 109 from being larger (see, for example, Japanese Patent Application Laid-open No. 2005-301439).
In the conventional voltage regulator, however, there is a problem in that an excessive overshoot occurs at the output terminal 109 when a power supply voltage becomes higher from a state in which the power supply voltage is low and the output terminal 109 outputs a voltage lower than a predetermined output voltage Vout (hereinafter referred to as “non-regulated state”). In order to prevent the excessive overshoot, it is necessary to increase the current supplied from the bias circuit 302 for the amplifier 301, and hence there is another problem in that the voltage regulator is increased in current consumption.